Open source software is all well and good, but what about open source CPUs?
So, this is free software clone of a certain famous board game, with some kind of pun in the title, right?
No, this has nothing to do with Risk. It’s all about CPU cores here – and specifically, RISC (reduced instruction set computing) ones. OpenRISC is a project that designs completely open processors, which you can study, modify, and have produced in factories. Well, providing you have enough money to do that, of course…
Hang on a minute! Reduced instruction set? Why would I want that? Give me more, more, more instructions!
Actually, RISC designs go back a long way, and have nothing to do with the overall power of a CPU. They’re all about designing the processor so that it has fewer jobs to do – but it can do them more quickly and efficiently than in other designs. Historically, x86 CPUs have been complicated beasts, with each generation adding more and more layers of cruft onto the original design. You end up with some CPU instructions taking just a few clock cycles to execute, whereas others take far longer.
RISC, however, opts for a much smaller range of instructions (and therefore fewer transistors on the chips), and these instructions are highly optimised. Fewer instructions doesn’t mean less capability though; after all, CPUs just move numbers around in memory and perform calculations on them. And today, RISC has won: ARM chips are built with RISC architecture and are absolutely everywhere, and even though x86 CPUs are still regarded as complex (Complex, rather than Reduced Instruction Set Computing) in their architectures, modern ones break instructions down into smaller components, in a RISC-like fashion.
OK, but CPUs are hardware – how do you make them open source? And why would you want to?
Yes, hardware doesn’t grow on trees (unless you have some fancy wood panelling for your PC case), so initially it might seem odd to apply FOSS principles to it. But consider designs: can you take your current PC or laptop processor, get a complete specification for it, change a few parts and make your own version? Unless you’re willing to pay giant licensing fees to Intel or AMD, this probably isn’t an option. And even then, you wouldn’t necessarily get to share your changes with the rest of the world.
Now, imagine if the entire design of your CPU were open. Imagine if the community could work together on improving its performance, features and power management. Imagine if this could work in tandem with an entirely free software stack, so that every byte and electron of your computer was free as in speech.
That sounds like heaven for Richard Stallman, but how many geeks really want to fiddle with CPU designs?
Just because it seems like a black art, or an obscure subject, it doesn’t mean that nobody is interested in it. On the contrary – at the time of writing, the third annual OpenRISC Conference (ORCONF 2014) was taking place in Munich, Germany. Forty developers from around the globe gathered together to discuss the current state of OpenRISC, share projects that they’re working on, and contemplate ideas for the future – see page 16 for a full report.
So, how are OpenRISC chips made? How is development done, and who produces them?
OpenRISC came to life in 1999, the work of a few computer science students in Slovenia, and received a small amount of financial backing in the early 2000s. Today, the OpenRISC project is much bigger and has a few chip designs (known as “cores”), but currently the focus is on the OpenRISC 1000, also known as OR1K: http://opencores.org/or1k. This CPU is focused on networking and embedded tasks, with special emphasis placed on simplicity and low power consumption. Its design is constructed using the Verilog hardware description language – and indeed, you can see the source code for yourself at https://github.com/openrisc/mor1kx/tree/master/rtl/verilog. This code is released under the GNU Lesser General Public Licence, so you’re free to base your own chip on it, as long as you make your designs available for everyone else.
For development purposes, the OR1K design can be implemented in FPGA (field-programmable gate array) development boards, which means you can hook up an OpenRISC processor to various peripherals and create a fully working computer. The GNU toolchain has been ported so that it can produce OpenRISC binaries, and work is underway to get LLVM/Clang to the same state as well. The Linux kernel itself has been able to run on OpenRISC since version 3.1, and a few other real-time operating systems such as eCos have OpenRISC ports as well.
OpenRISC is popular in embedded devices, and at ORCONF one developer talked about a project using OpenRISC chips in TV set-top boxes to convert satellite video data to internet streaming formats. Other embedded chips had been considered, but it was important for the set-top box manufacturer that the chips could run the Linux kernel, so OpenRISC was chosen.
Another area in which OpenRISC is well known is academia. The Technical University of Munich uses it in research (which is why the conference was held in the city), while many other universities teach courses based on it.
What about the chip in the real world, though – are there any commercial implementations?
You bet! This isn’t just a play toy for hackers and students. OpenRISC has been implemented in many SoC (system on a chip) designs – that is, chips that include all the components needed for a standalone computer. Most notably, Samsung has used it in various digital TV models, while the Allwinner A31, a SoC used in a large range of mobile phones, tablets and smart TVs, has an OpenRISC core doing power management work.
OpenRISC has even gone into space as part of the TechEdSat project, which is a satellite designed by students at San Jose State University – it needed to be cheap, so OpenRISC was a natural choice. It could be used in many other devices and projects as well, that we don’t even know about, just as Linux and the BSDs are often chugging away inside networking and embedded hardware, without any fanfare.
Is OpenRISC finished, or is it still a work in progress?
With 80,000 lines of Verilog behind the design, there’s still plenty of room for tweaks, performance improvements and power savings. A team of developers is beavering away on a new CPU pipeline – that is, the series of stages used to process instructions. Ideally, it will support out-of-order execution, along with dynamic branch prediction. Another topic that came up at the conference was improving the 64-bit version of the chip. There’s even some interest in porting FreeBSD to OpenRISC, although we’d wager that NetBSD will get there first, given that it already runs on a staggering number of platforms…
OK, you’ve sufficiently whetted my appetite, and now I want to make big bucks as a CPU designer. Where do I start?
Well, we can’t guarantee that you’ll be the Chief CPU Architect at Intel after playing around with OpenRISC for a few months, but it’s a great way to dip your toes into the vast wold of processor design. A good place to begin is the Getting Started guide at http://kevinmehall.net/openrisc/guide – and note the requirements in particular. You should have a solid grounding in the workings of a Linux installation, along with knowledge of Verilog and C (the language used to code the Linux kernel).
The guide also explains how to run or1ksim, an OpenRISC CPU emulator, and how to use the chip on an FPGA development board. You can pick up one of these boards for around £50 to £100; see http://opencores.org/or1k/FPGA_Development_Boards for a list of boards that work with OpenRISC. But if you really want to dive in at the deep end, try the Architecture Manual at http://tinyurl.com/qj6pjfc – just bear in mind that it’s 358 pages long!